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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad7896 2.7 v to 5.5 v, 12-bit, 8 s adc in 8-lead soic/pdip general description the ad7896 is a fast, 12-bit adc that operates from a single 2.7 v to 5.5 v supply and is housed in small 8-lead pdip and 8-lead soic packages. the part contains an 8 s successive approximation adc, an on-chip track-and-hold amplifier, an on-chip clock, and a high speed serial interface. output data from the ad7896 is provided via a high speed, serial interface port. this 2-wire serial interface has a serial clock input and a serial data output with the external serial clock accessing the serial data from the part. in addition to the traditional dc accuracy specifications, such as linearity, full-scale, and offset errors, the ad7896 is also speci- fied for dynamic performance parameters, including harmonic distortion and signal-to-noise ratio. the part accepts an analog input range of 0 v to v dd and operates from a single 2.7 v to 5.5 v supply, consuming only 9 mw typical. the v dd input is also used as the reference for the part so that no external reference is required. the ad7896 features a high sampling rate mode and, for low power applications, a proprietary automatic power-down mode where the part automatically goes into power-down once conver- sion is complete and wakes up before the next conversion cycle. the part is available in a small, 8-lead, 0.3'' wide, plastic or hermetic dual-in-line package (pdip) and in an 8-lead, small outline ic (soic). features 100 khz throughput rate fast 12-bit sampling adc with 8 s conversion time 8-lead pdip and soic single 2.7 v to 5.5 v supply operation high speed, easy-to-use serial interface on-chip track-and-hold amplifier analog input range is 0 v to supply high input impedance low power: 9 mw typ functional block diagram clock 12-bit adc output register track-and-hold ad7896 v in c onvst v dd agnd dgnd busy sclk sdata product highlights 1. complete, 12-bit adc in an 8-lead package. the ad7896 contains an 8 s adc, a track-and-hold ampli- fier, control logic, and a high speed serial interface, all in an 8-lead pdip. the v dd input is used as the reference for the part, so no external reference is needed. this offers consider- able space saving over alternative solutions. 2. low power, single-supply operation. the ad7896 operates from a single 2.7 v to 5.5 v supply and consumes only 9 mw typical. the automatic power- down mode, where the part goes into power down once conversion is complete and wakes up before the next con- version cycle, makes the ad7896 ideal for battery-powered or portable applications. 3. high speed serial interface. the part provides high speed serial data and serial clock lines allowing for an easy, 2-wire serial interface arrangement.
rev. c e2e ad7896especifications (v dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v. all specifications t min to t max , unless otherwise noted.) test conditions/ parameter a version 1 b version j version s version unit comments dynamic performance 2 signal-to-(noise + distortion) ratio 3 @ 25 c7070 70 typ 70 db min f in = 10 khz sine wave, f sample = 100 khz t min to t max 70 db min total harmonic distortion (thd) 3 ? 80 ? 80 ? 80 typ ? 80 db max f in = 10 khz sine wave, f sample = 100 khz peak harmonic or spurious noise 3 ? 80 ? 80 ? 80 typ db max f in = 10 khz sine wave, f sample = 100 khz intermodulation distortion (imd) 3 fa = 9 khz, fb = 9.5 khz, f sample = 100 khz second order terms ? 80 ? 80 ? 80 typ ? 80 db max third order terms ? 80 ? 80 ? 80 typ ? 80 db max dc accuracy resolution 12 12 12 12 bits minimum resolution for which no missing codes are guaranteed 12 12 12 12 bits relative accuracy 3 1 1/2 1 1lsb max differential nonlinearity 3 1 1 1 1lsb max positive full-scale error 3 3 1.5 3 3lsb max unipolar offset error 4 4 5 4lsb maxv dd = 5 v 10% 4 3 5 4lsb maxv dd = 2.7 v to 3.6 v analog input input voltage range 0 to +v dd 0to+v dd 0to+v dd 0 to +v dd v input current 2 2 2 5 a max logic inputs input high voltage, v inh 2.0 2.0 2.0 2.0 v min v dd = 2.7 v to 3.6 v 2.4 2.4 2.4 2.4 v dd = 5 v 10% input low voltage, v inl 0.8 0.8 0.8 0.8 v max input current, i in 10 10 10 10 a max v in = 0 v to v dd input capacitance, c in 4 10 10 10 10 pf max logic outputs output high voltage, v oh 2.4 2.4 2.4 2.4 v min i source = 400 a output low voltage, v ol 0.4 0.4 0.4 0.4 v max i sink = 1.6 ma output coding straight (natural) binary conversion rate conversion time mode 1 operation 8 8 8 8.5 s max mode 2 operation 5 14 14 14 14.5 s max track-and-hold acquisition time 3 1.5 1.5 1.5 1.5 s max
rev. c ad7896 e3e test conditions/ parameter a version 1 b version j version s version unit comments power requirements v dd 2.7/5.5 2.7/5.5 2.7/5.5 2.7/5.5 v min/max i dd 444 4 ma max digital input @ dgnd, v dd = 2.7 v to 3.6 v 555 5 ma max digital inputs @ dgnd, v dd = 5 v 10% power dissipation 10.8 10.8 10.8 10.8 mw max v dd = 2.7 v, typically 9 mw power-down mode digital inputs @ dgnd i dd @ 25 c 555 typ5 a max v dd = 2.7 v to 3.6 v t min to t max 15 15 75 75 a max v dd = 2.7 v to 3.6 v i dd @ 25 c505 05050 a max v dd = 5 v 10% t min to t max 150 150 500 500 a max v dd = 5 v 10% power dissipation @ 25 c 13.5 13.5 13.5 13.5 w max v dd = 2.7 v notes 1 temperature ranges are as follows: a, b versions: ? 40 c to +85 c; j version: 0 c to +70 c; s version: ? 55 c to +125 c. 2 applies to mode 1 operation. see the section on operating modes. 3 see terminology. 4 sample tested @ 25 c to ensure compliance. 5 this 14 s includes the wake-up time from standby. this wake-up time is timed from the rising edge of convst convst convst t n convst s av v sv tcc convst 2 2 2 2 sc 2 2 2 sc atsc v v v 2vv tsc rtsc nots s2 cav v 2 tscc tsc ssi v2 v vt t tiincaractristics v 2vvann v 1.6v 1.6ma 400 a 50pf to output pin figure 1. load circuit for access time and bus relinquish time
rev. c e4e ad7896 absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . ? 0.3 v to +7 v analog input voltage to agnd . . . . . . ? 0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . . ? 0.3 v to v dd + 0.3 v digital output voltage to dgnd . . . . . ? 0.3 v to v dd + 0.3 v operating temperature range commercial (j version) . . . . . . . . . . . . . . . . . 0 c to +70 c industrial (a, b versions) . . . . . . . . . . . . . . ? 40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . . ? 55 c to +125 c storage temperature range . . . . . . . . . . . . . ? 65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c pdip package, power dissipation . . . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 125 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . 50 c/w lead temperature (soldering, 10 sec) . . . . . . . . . . . . 260 c soic package, power dissipation . . . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 160 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000 v * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature linearity snr package model range error (lsb) (db) option * ad7896an ? 40 c to +85 c 170 n-8 ad7896bn ? 40 c to +85 c 1/2 70 n-8 ad7896ar ? 40 c to +85 c 170r-8 ad7896ar-reel ? 40 c to +85 c 170r-8 ad7896ar-reel7 ? 40 c to +85 c 170r-8 ad7896br ? 40 c to +85 c 1/2 70 r-8 AD7896BR-REEL ? 40 c to +85 c 1/2 70 r-8 AD7896BR-REEL7 ? 40 c to +85 c 1/2 70 r-8 ad7896jr 0 c to +70 c 170r-8 ad7896jr-reel 0 c to +70 c 170r-8 ad7896sq ? 55 c to +125 c 170 q-8 eval-ad7896cb evaluation board * n = pdip; q = cerdip; r = soic. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7896 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. c ad7896 e5e pin configuration 1 2 3 4 8 7 6 5 top view (not to scale) ad7896 v in sdata dgnd convs t busy v dd agnd sclk pin function descriptions pin no. mnemonic description 1v in analog input. the analog input range is 0 v to v dd . 2v dd positive supply voltage, 2.7 v to 5.5 v. 3 agnd analog ground. ground reference for track-and-hold, comparator, and dac. 4 sclk serial clock input. an external serial clock is applied to this input to obtain serial data from the ad7896. a new serial data bit is clocked out on the falling edge of this serial clock. data is guaranteed valid for 10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used. the serial clock input should be taken low at the end of the serial data transmission. 5 sdata serial data output. serial data from the ad7896 is provided at this output. the serial data is clocked out by the falling edge of sclk, but the data can also be read on the falling edge of the sclk. this is possible because data bit n is valid for a specified time after the falling edge of the sclk (data hold time) and can be read before data bit n+1 becomes valid a specified time after the falling edge of sclk (data access time) (see figure 4). sixteen bits of serial data are provided with four leading zeros followed by the 12 bits of conversion data. on the 16th falling edge of sclk, the sdata line is held for the data hold time and then disabled (three-stated). output data coding is straight binary. 6 dgnd digital ground. ground reference for digital circuitry. 7 convst cso i convst i convst s tsts convst
rev. c e6e ad7896 terminology relative accuracy this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale (which is v in = agnd + 1/2 lsb), a point 1/2 lsb below the first code transi- tion (00 . . . 000 to 00 . . . 001), and full scale (which is v in = agnd + v dd ? 1/2 lsb), a point 1/2 lsb above the last code transition (11 ... 110 to 11 ... 111). differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. unipolar offset error this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal v in voltage (agnd + 1 lsb). positive full-scale error this is the deviation of the last code transition (11 ... 110 to 11 . . . 111) from the ideal (v in = agnd + v dd ? 1 lsb) after the offset error has been adjusted out. track-and-hold acquisition time track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion (the point at which the track-and-hold returns into track mode). it also applies to a situation where there is a step input change on the input voltage applied to the selected v in input of the ad7896. it means that the user must wait for the duration of the track-and-hold acquisi- tion time after the end of conversion or after a step input change to v in before starting another conversion, to ensure the part operates to specification. signal-to-(noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fun- damental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza- tion process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to-(noise + distortion) = ( 6.02 n + 1.76 ) db thus, for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7896, it is defined as: thd db vvvvv v () log = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7896 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified sepa- rately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in db.
rev. c ad7896 e7e converter details the ad7896 is a fast, 12-bit adc that operates from a single 2.7 v to 5.5 v supply. it provides the user with a track-and- hold, adc, and serial interface logic functions on a single chip. the adc section of the ad7896 consists of a conven- tional successive approximation converter based on an r-2r ladder structure. the internal reference for the ad7896 is derived from v dd , which allows the part to accept an analog input range of 0 v to v dd . the ad7896 has two operating modes: the high sampling mode and the auto sleep mode where the part automatically goes into sleep after the end of conversion. these modes are discussed in more detail in the timing and control section. a major advantage of the ad7896 is that it provides all of the preceding functions in an 8-lead package, pdip or soic. this offers the user considerable space saving advantages over alterna- tive solutions. the ad7896 consumes only 9 mw typical, making it ideal for battery-powered applications. conversion is initiated on the ad7896 by pulsing the convst o convst t c a (14 s for the auto sleep mode), and the track-and-hold acquisition time is 1.5 s. to obtain optimum performance from the part, the read operation should not occur during the conversion or during 400 ns prior to the next conversion. this allows the part to operate at throughput rates up to 100 khz and achieves data sheet specifications (see the timing and control section). circuit description analog input section the analog input range for the ad7896 is 0 v to v dd. the v in pin drives the input to the track-and-hold amplifier directly. this allows for a maximum output impedance of the circuit driving the analog input of 1 k . this ensures that the part will be settled to 12-bit accuracy in the 1.5 s acquisition time. this input is benign with dynamic charging currents. the designed code transitions occur on successive integer lsb values (i.e., 1 lsb, 2 lsb, 3 lsb, . . . , fs ? 1 lsb). output coding is straight (natural) binary with 1 lsb = fs/4096 = 3.3 v/4096 = 0.81 mv. the ideal input/output transfer function is shown in table i. table i. ideal input/output code table for the ad7896 analog input 1 code transition +fsr ? 1 lsb 2 (3.299194) 111 . . . 110 to 111 . . . 111 +fsr ? 2 lsb (3.298389) 111 . . . 101 to 111 . . . 110 +fsr/2 ? 3 lsb (3.297583) 111 . . . 100 to 111 . . . 101 agnd + 3 lsb (0.002417) 000 . . . 010 to 000 . . . 011 agnd + 2 lsb (0.001611) 000 . . . 001 to 000 . . . 010 agnd + 1 lsb (0.000806) 000 . . . 000 to 000 . . . 001 notes 1 fsr is full-scale range and is 3.3 v with v dd = +3.3 v. 2 1 lsb = fsr/4096 = 0.81 mv with v dd = +3.3 v. track-and-hold section the track-and-hold amplifier on the analog input of the ad7896 allows the adc to accurately convert an input sine wave of full- scale amplitude to 12-bit accuracy. the input bandwidth of the track-and-hold is greater than the nyquist rate of the adc even when the adc is operated at its maximum throughput rate of 100 khz (i.e., the track-and-hold can handle input frequencies in excess of 50 khz). the track-and-hold amplifier acquires an input signal to 12-bit accuracy in less t han 1.5 s. the operation of the track-and- hol d is essentially transparent to the user. w ith the high sampling operating mode, the track-and-hold amplifier goes from its tracking mode to its hold mode at the start of conversion (i.e., the rising edge of convst t convst a s t convst convst convst o s tc 2 ai convst a o convst v t a t aa satai convst a convst t i v t a t t a
rev. c e8e ad7896 operating modes mode 1 operation (high sampling performance) the timing diagram in figure 2 is for optimum performance in operating mode 1 where the falling edge of convst t convst s ts convst aat v t convst t 2oasc t o2 s t convert = 8 s busy sclk serial read operation conversion ends 8 s later output serial shift register is reset conversion is initiated and track-and-hold goes into hold t 1 = 40ns min 400ns min t 1 t convert = 8 s read operation should end 400ns prior to next falling edge of convst c onvst 2 tos convst busy sclk serial read operation conversion ends 14s later read operation should end 400ns prior to next fa lling edge of convst output serial shift register is reset part wakes up conversion is initiated track-and- hold goes into hold t 1 = 6 s w ake-up time t 1 t convert = 14 s 400ns min figure 3. mode 2 timing diagram where automatic sleep function is initiated before the next conversion takes place. this is achieved by keeping convst t convst t t convst convst sn convst convst convst t convst i s t v convst t
rev. c ad7896 e9e serial interface the serial interface to the ad7896 consists of three wires: a serial clock input (sclk), the serial data output (sdata), and a conversion status output (busy). this allows for an easy-to- use interface to most microcontrollers, dsp processors, and shift registers. figure 4 shows the timing diagram for the read operation to the ad7896. the serial clock input (sclk) provides the clock source for the serial interface. serial data is clocked out from the sdata line on the falling edge of this clock and is valid on both the rising and falling edges of sclk. the advantage of having the data valid on both the rising and falling edges of the sclk is to give the user greater flexibility in interfacing to the part and so that a wider range of microprocessor and microcontroller inter- faces can be accommodated. this also explains the two timing figures t 4 and t 5 that are quoted on the diagram. the time t 4 speci- fies how long after the falling edge of the sclk that the next data bit becomes valid, whereas the time t 5 specifies how long after the falling edge of the sclk that the current data bit is valid for. the first leading zero is clocked out on the first rising edge of sclk; note that the first zero may be valid on the first falling edge of sclk even though the data access time is specified at 60 ns (5 v [a, b, j versions only]) for the other bits (and the sclk high time will be 50 ns with a 10 mhz sclk). the reason that the first bit will be clocked out faster than the other bits is due to the intern al architecture of the part. sixteen clock pulses must be provided to the part to access the full conversion result. the ad7896 provides four leading zeros followed by the 12-bit conversion result starting with the msb (db11). the last data bit to be clocked out on the penultimate falling clock edge is the lsb (db0). on the 16th falling edge of sclk, the lsb (db0) will be valid for a specified time to allow the bit to be read on the falling edge of sclk, and then the sdata line is disabled (three-stated). after this last bit has been clocked out, the sclk input should remain low until the next serial data read opera- tion. if there are extra clock pulses after the 16th clock, the ad7896 will start over again with outputting data from its out- put register, and the data bus will no longer be three-stated even when the clock stops. provided the serial clock has stopped before the next falling edge of convst a convst sc convst t t 2a sc tscv 2v sc v2va v2 vs n vasc asic at sc ta sata t convst sct convst icrorocssoricrocontrorintrac t a s a s ta a ai a t t a t 2 4 leading zeros dout (o/p) sclk ( i/p) t 6 123 45615 16 db0 db10 db11 three-state t 5 t 3 t 4 three-state t 2 = t 3 = 40ns min, t 4 = 60ns max, t 5 = 10ns min, t 6 = 50ns max @ 5v, a, b, versions figure 4. data read operation
rev. c e10e ad7896 the busy line can be connected to the irq c t tc aa ta c sdata busy sck miso sclk pc2 or irq 68hc11/l11 ad7896 figure 6. ad7896 to 68hc11/l11 interface ad7896eadsp-2103/adsp-2105 interface an interface circuit between the ad7896 and the adsp- 2103/adsp-2105 dsp processor is shown in figure 7. in the interface shown, the rfs1 output from the adsp-2103/ adsp-2105s sport1 serial port is used to gate the serial clock (sclk1) of the adsp-2103/adsp-2105 before it is applied to the sclk input of the ad 7896. the rfs1 output is configured for active high operation. the busy line from the ad7896 is connected to the irq2 as2as2 as2as2t a a tsataa ras2as2 tscrs as2as2 sc rs t sc as2as2t a va sca an scas2 t as2sc sc t a as 2rs ai 2 as2sc a v ta a aan t a ts sa2 s tsint t nas st a t aa ta sclk busy p3.0 p3.1 8x51/l51 ad7896 sdata p1.2 or int1 figure 5. ad7896 to 8x51/l51 interface ad7896e68hc11/l11 interface an interface circuit between the ad7896 and the 68hc11/l11 microcontroller is shown in figure 6. for the interface shown, the 68hc11/l11 spi port is used and the 68hc11/l11 is con- figured in its single-chip mode. the 68hc11/l11 is configured in the master mode with its cpol bit set to a logic 0 and its cpha bit set to a logic 1. as with the previous interface, the diagram shows the simplest form of the interface, where the ad7896 is the only part connected to the serial port of the 68hc11/l11 and, therefore, no decoding of the serial read operations is required. once again, to chip select the ad7896 in systems where more than one device is connected to the 68hc11/l11 serial port, a port bit, configured as an output, from one of the 68hc11/l11 parallel ports can be used to gate on or off the serial clock to the ad7896. a simple and function on this port bit and the serial clock from the 68hc11/l11 will provide this function. the port bit should be high to select the ad7896 and low when it is not selected. the end of conversion is monitored by using the busy signal which is shown in the interface diagram of figure 6. with the busy line from the ad7896 connected to the port pc2 of the 68hc11/l11, the busy line can be polled by the 68hc11/l11.
rev. c ad7896 e11e figure 9 shows a histogram plot for 8192 conversions of a dc input using the ad7896 with a 3.3 v supply. the analog input was set at the center of a code transition. it can be seen that almost all the codes appear in the one output bin, indicating very good noise performance from the adc. the rms noise performance for the ad7896 for the plot below was 111 v. 9000 0 2000 1000 3000 4000 5000 6000 7000 8000 1005 1006 code f sample = 95khz, f sclk = 8.33mhz, ain centered on code 1005 rms noise = 0.138 lsb occurrence figure 9. histogram of 8192 conversions of a dc input the same data is presented in figure 10 as in figure 9, except that in this case, the output data read for the device occurs during conversion. this has the effect of injecting noise onto the die while bit decisions are being made and this increases the noise generated by the ad7896. the histogram plot for 8192 conversions of the same dc input now shows a larger spread of codes with the rms noise for the ad7896 increasing to 279 v. this effect will vary depending on where the serial clock edges appear with respect to the bit trials of the conversion process. it is possible to achieve the same level of performance when reading during conversion as when reading after conver- si on, depending on the relationship of the serial clock edges to the bit trial points. 8000 0 2000 1000 1004 4000 3000 5000 6000 7000 1005 1006 code occurrence f sample = 95khz, f sclk = 8.33mhz , ain centered on code 1005, rms noise = 0.346 lsb figure 10. histogram of 8192 conversions with read during conversion an alternative scheme is to configure the adsp-2103/adsp-2105 such that it accepts an external noncontinuous serial clock. in th is case, an external noncontinuous serial clock is provided that drives the serial clock inputs of both the adsp-2103/adsp-2105 and the ad7896. in this scheme, the serial clock frequency is limited to 10 mhz by the ad7896. sdata busy sclk1 dr1 adsp-2103/ adsp-2105 ad7896 sclk irq2 rfs1 figure 7. ad7896 to adsp-2103/adsp-2105 interface ad7896edsp56002/l002 interface figure 8 shows an interface circuit between the ad7896 and the dsp56002/l002 dsp processor. the dsp56002/l002 is con- figured for normal mode asynchronous operation with gated clock. it is also set up for a 16-bit word with sck as gated clock output. in this mode, the dsp56002/l002 provides 16 serial clock pulses to the ad7896 in a serial read operation. the dsp56002/l002 assumes valid data on the first falling edge of sck so the interface is simply 2-wire as shown in figure 8. the busy line from the ad7896 is connected to the moda/ irqa s22 t sdata busy sck sdr dsp56002/l002 ad7896 sclk moda/ irqa as22i aroranc ta2 ac tac2 t sn 2 s n iac t iaca 2t n s 2
rev. c e12e ad7896 dynamic performance (mode 1 only) with a combined conversion and acquisition time of 9.5 s, the ad7896 is ideal for wide bandwidth signal processing applications. these applications require information on the adc ? s effect on the spectral content of the input signal. signal -t o-(noise + d istortion), t otal harmonic distortion, peak harmonic or spurious noise, and intermodulation distortion are all specified. figure 11 shows a typical fft plot of a 10 khz, 0 v to 3.3 v input after being digi- tized by the ad7896 operating at a 102.4 khz sampling rate. the signal-to-(noise + distortion) ratio is 71.5 db and the total harmonic distortion is ? 8 2.4 db. ?0 ?120 51200 ?60 ?100 10240 ?80 0 ?20 ?40 40960 30720 20480 frequency (hz) db f sample = 102.4khz f in = 10khz snr = 71.54db thd = ?82.43db figure 11. ad7896 fft plot effective number of bits the formula for signal-to-(noise + distortion) ratio (see the terminology section) is related to the resolution or number of bits in the converter. rewriting the formula below gives a mea- sure of performance expressed in effective number of bits ( n ) n = ( snr 1.76)/6.02 where snr is the signal-to-(noise + distortion) ratio. the effective number of bits for a device can be calculated from its measured signal-to-(noise + distortion) ratio. figure 12 shows a typical plot of effective number of bits versus frequency for the ad7896 from dc to f sampling /2. the sampling frequency is 102.4 khz. the plot shows that the ad7896 converts an input sine wave of 51.2 khz to an effective numbers of bits of 11.25, which equates to a signal-to-(noise + distortion) level of 69 db. 12.00 0 51.2 25.6 11.75 11.50 11.25 11.00 input frequency (khz) effective number of bits figure 12. effective number of bits vs. frequency power considerations in the automatic power-down mode, the part can be operated at a sample rate that is considerably less than 100 khz. in this case, the power consumption will be reduced and will depend on the sample rate. figure 13 shows a graph of the power con- sumption versus sampling rates from 10 hz to 1 khz in the automatic power-down mode. the conditions are 2.7 v supply, 25 c, serial clock frequency of 8.33 mhz, and the data was read after conversion. 200 0 1000 120 40 100 80 10 160 sampling rate in hz power ( w) f sclk = 8.33mhz figure 13. power vs. sample rate in auto power- down mode
rev. c ad7896 e13e 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095aa 0.015 (0.38) min 8-lead ceramic dual in-line package [cerdip] (q-8) dimensions shown in inches and (millimeters) 1 4 85 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa outline dimensions
rev. c e14e ad7896 revision history location page 7/03?data sheet changed from rev. b to rev. c. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 added esd warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
e15e
c01363e0e7/03(c) e16e

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